NVIDIA (NVDA): Where the AI-Infrastructure Profits Concentrate, and Whether They Hold

Thesis

The money has quietly left the GPU die — the silicon chip itself, as distinct from the machinery built around it. NVIDIA's profit that lasts now sits in the rack-scale interconnect and the co-designed system around it — the wiring and switching that make a whole cabinet of chips behave as one computer — which is why the layer most exposed over the next three years is the gross margin, not the software estate the consensus worries about: sandwiched between a memory oligopoly selling on take-or-pay floors and three customers who supply 54% of revenue.

Start with what the market already knows and has paid for. NVIDIA reported $81.6 billion of revenue in the quarter ended 26 April 2026, up 85% from a year earlier, with Data Center at $75.2 billion and a 74.9% GAAP gross margin (CFO Commentary, Q1 FY2027, 20 May 2026). It guided the July quarter to $91.0 billion. At $216.75 a share on 11 August 2026 the company carries a ~$5.25 trillion market capitalisation and roughly 33x trailing earnings (stockanalysis.com, 11 Aug 2026). None of that is in dispute. Growth of that magnitude, at that margin, is not a thesis — it is a fact pattern, and the market has priced the fact pattern.

The interesting question sits one level down. Revenue growth is not pricing power. Market leadership is not a defended position either, and a lead whose width depends on a rival's delay is a lead, not an annuity. So: which layers of this stack actually keep excess profit after a competent, well-capitalised competitor arrives — and which merely look defended because nobody has yet had the time, the capital, and the reason to attack them all at once?

The answer that falls out of the filings is not the consensus one. CUDA — the programming layer NVIDIA introduced in 2006 and now used by more than 7.5 million developers (NVIDIA FY2026 Form 10-K, Item 1) — is a genuine asset that is no longer the binding constraint on a buyer's decision. AMD's ROCm — AMD's answer to CUDA, the software layer that lets ordinary programs run on its GPUs — now has upstreamMerged into the official project itself rather than maintained as a private fork. Upstream support means the AMD path ships with PyTorch by default, so a user does not have to hunt down a special build or maintain their own patches — which is most of what made earlier "AMD works too" claims hollow. PyTorchThe open-source framework most AI code is now written in. A developer describes the model in PyTorch; PyTorch works out how to run it on whatever chip is underneath. Because it supports several hardware back-ends, code written in PyTorch rather than directly in CUDA is portable — which is why the framework layer, not the chip layer, is where lock-in is won or lost. support, a PyTorch MonarchA PyTorch project for driving one very large training job across a whole cluster from a single controller. It matters here because software stacks usually break at cluster scale, not on one chip — so a port of Monarch is a claim about the hard case. port for ROCm production training, and AMD's own vLLMA widely used open-source engine for serving models — the software that answers real user requests efficiently across a fleet of accelerators. Support for it is the practical test of whether a chip can be put into production, as opposed to run in a benchmark. optimisation path for MI300/MI325/MI350/MI355-class GPUs (PyTorch local install docs, retrieved 11 Aug 2026; PyTorch Foundation, 6 Jul 2026; AMD ROCm vLLM optimisation docs, 29 May 2026), and the largest buyers write against frameworks, not against CUDA. What has not been replicated is the thing that is boring to write about: a 72-GPU coherent NVLink domain — seventy-two chips wired together so tightly that software can address them as one very large accelerator sharing one pool of memory — the switch siliconThe chips inside the network gear that decide, in nanoseconds, which wire a piece of data goes down next. A switch is to a data centre what a junction is to a railway; the silicon is the part that does the switching, and it is designed, not bought off a shelf. underneath it, the Ethernet fabric outside it — the network that ties those racks into a cluster — and the ability to ship all of it as one manufactured, serviceable rack. NVIDIA's Data Center networking line grew 199% year over year in the April quarter, to $14.8 billion — two and a half times the growth rate of compute. The market treats networking as a rounding error attached to the GPU. It is the opposite: increasingly the GPU is the thing that pulls the network through.

The second finding cuts the other way. In the same window, Micron reported an 84.6% gross margin and SK hynix a 76.3% operating margin — each above NVIDIA's own. Memory has converted itself from the industry's most brutally cyclical business into a contracted one, with multi-year take-or-pay agreements — the buyer pays for the volume it has committed to whether it takes the chips or not — carrying floor prices. That matters far more than it sounds. It means NVIDIA now buys its scarcest input on terms that are sticky downward while it sells its output on purchase orders that customers "can generally cancel, change, or delay… with little notice… and without penalty" (FY2026 10-K, Item 1A). In a boom that asymmetry is invisible. In a digestion — the pause while buyers work through capacity they have already bought, which is not the same thing as demand collapsing — it is the whole story.

■ Executive takeaways

Seven ranked, checkable conclusions the body proves. Confidence tags follow the six-level scale used throughout.

1. 1The most defended layer is interconnect, not CUDA. Data Center networking revenue reached $14.8bn in Q1 FY2027, up 199% y/y against compute's 77% — and AWS has said its Trainium4The fourth generation of Amazon's own AI training chip, designed in-house as an alternative to buying NVIDIA GPUs for its cloud. will support NVLink Fusion — NVIDIA licensing the in-rack fabric so that somebody else's accelerator can plug into it — meaning a rival accelerator will plug into NVIDIA's fabric rather than replace it. High
2. 2The profit is migrating upstream faster than sideways. Micron's gross margin of 84.6% (quarter ended 28 May 2026) now exceeds NVIDIA's 74.9%, and its largest supply agreements carry floor prices — converting NVIDIA's biggest input cost from cyclical to sticky. High
3. 3Customer concentration, not competition, is the near-term structural risk. Three direct customers were 54% of revenue in Q1 FY2027 (21/17/16), against two customers at 36% for all of FY2026. The buyer side is consolidating faster than the supplier side is being contested. High
4. 4Google — not AMD — is the first credible challenge to the full-stack model. Alphabet's 10-Q now books "product revenues primarily from the sale of TPU systems" and confirms signed agreements to supply TPUsTensor Processing Units — Google's own AI accelerator chips, designed in-house and used inside Google for years before being offered to anyone else. They are the most complete alternative to an NVIDIA GPU in existence, because Google also built the interconnect and the software around them. for on-premises deployment, with the significant majority of revenue landing in 2027; Google Cloud's own TPU page also shows Ironwood generally available and TPU 8i/8t as coming soon (Google Cloud TPU page, retrieved 11 Aug 2026; Google TPU7x docs, retrieved 11 Aug 2026). That is merchant silicon — chips sold to outside buyers, rather than built only for the maker's own data centres — from a company with its own frontier modelOne of the handful of largest and most capable AI models at the leading edge of what is technically possible. Frontier models set the hardware requirements everyone else follows, so a company that has one knows what its chips must be able to do before anyone else does.. Moderate–High
5. 5The Groq transaction reveals what NVIDIA actually fears: inference ASICs. An ASIC is a chip hard-wired for a single job — cheaper and faster at that job, and useless at anything else. Disclosed consideration was $17.0bn ($13.0bn at close plus $4bn payable), of which $14.4bn was booked as goodwill for "workforce and future development" — and the technology shipped as "Groq 3 LPX" inside the Vera Rubin rack within six months. Two US senators have asked whether the structure was designed to avoid premerger review. Moderate
6. 6NVIDIA is no longer capital-light, and that changes the downside. Supply and capacity commitments stood at $119bn at 26 April 2026 — $95bn payable within the fiscal year — plus $30bn of multi-year cloud commitments and $32.4bn of leases yet to commence. Roughly 47% of trailing-twelve-month revenue is already committed to suppliers. High
7. 7The valuation is not the problem; the duration assumption is. At 33x trailing and ~22x forward earnings, the multiple demands neither heroic growth nor heroic margins — it demands that 75% gross margins survive four more years. That is the single assumption on which the equity turns. Moderate

All five from NVIDIA's Q1 FY2027 Form 10-Q and CFO Commentary, period ended 26 April 2026.

01
The arc: three bets, thirty years apart

NVIDIA's position was not won in 2023. It was won by three decisions — a programmable architecture, a free software layer nobody asked for, and a networking acquisition everybody thought was expensive.

The company was incorporated in California in April 1993 and reincorporated in Delaware in 1998; it invented the GPU (graphics processing unit, a chip built to run thousands of small calculations in parallel rather than a few large ones in sequence) in 1999. That much is corporate history. The consequential part starts in 2006, when NVIDIA introduced CUDA (Compute Unified Device Architecture — a way to write ordinary programs that run on the graphics chip) and, in the company's own words, "opened the parallel processing capabilities of our GPU to a broad range of compute-intensive applications, paving the way for the emergence of modern AI" (FY2026 10-K, Item 1).

For roughly six years CUDA generated no identifiable profit. It was a tax on gross margin — silicon area spent on general-purpose compute that gaming customers did not need, and a software organisation funded out of a graphics-card business. What made it pay was not foresight about neural networks. It was that the cost of being wrong was small and the cost of being right, if anyone ever needed cheap parallel compute, was that they would have to come through NVIDIA. That is the structure of nearly every durable franchise: a cheap option on a scarce right, held long enough for the world to need it.

The world needed it in 2012, when AlexNet — trained on NVIDIA GPUs — won the ImageNet image-recognition competition, an event the company still calls "the 'Big Bang' moment of AI" in its annual report. Then a second, deliberate bet: the first Tensor Core GPU in 2017, built specifically for neural-network arithmetic. Then the third, and the most underrated: the acquisition of Mellanox in 2020, which "expanded our offerings to include networking, enabled our platforms to be data center scale, and led to the introduction of a new processor class — the data processing unit, or DPU."

Enabled our platforms to be data center scale. That is the company saying, in a filing, where it thinks the leverage came from. Everything after — Grace, the first data-centre CPU in 2023; Blackwell in 2024, wiring 36 CPUs and 72 GPUs into one liquid-cooled rack; Blackwell Ultra in FY2026; Vera Rubin in 2026 — is the same idea compounding. The unit of sale stopped being a chip.

02
What accelerated computing actually is

A large language model is, at the level that matters for silicon, a very long sequence of matrix multiplications. Training adjusts several hundred billion numbers by repeatedly multiplying matrices and propagating errors backwards. Inference — actually answering a question — runs the same multiplications forward, once per generated token, with the model's weights held in memory. A token is the unit a model reads and writes in — roughly a short word or a fragment of one, so a paragraph of output is a few hundred of them. It is also the unit the industry meters and sells in, which is why cost per token and tokens per second per rack recur later as the terms on which this entire business is judged. Both are embarrassingly parallelA problem that splits cleanly into thousands of pieces that can be worked on at the same time without waiting for each other. It is the property that makes a chip with thousands of small cores useful, and it is why AI runs on GPUs rather than on ordinary processors. and both are, in practice, limited less by arithmetic than by how fast numbers can be moved: from memory to the chip, and from chip to chip.

Everything downstream turns on one technical fact. Modern AI silicon is rarely compute-bound. It is bandwidth-bound. That is why high-bandwidth memory (HBM — DRAMDynamic random-access memory: the ordinary working memory of any computer, the place data sits while it is being used. HBM is DRAM built in stacks and bolted directly onto the processor package, which buys enormous speed at enormous cost. dies stacked vertically and wired to the processor through the silicon itself) is the scarce input, and why the interconnect — the links that carry data from one chip to the next — is not plumbing but architecture. A model too large for one chip's memory must be split across many, and every split turns a memory access into a network hop. Whoever controls the speed of that hop controls how large a model can be run economically.

That network has a name, and it is worth pausing on, because the argument of this brief is built from it. The switches, the cables, the protocol and the software that keep thousands of accelerators exchanging results in step are collectively called a fabric. A fabric is not cabling bought by the metre; it is a designed system, and its speed sets the size of the model that can be trained or served at all. That is what is meant later by saying the fabric is architecture rather than plumbing: change it and you change what the machine can do, which is not true of the wiring in an ordinary data centre.

1. 01
   Weights in HBM

   Model parameters sit in stacked memory beside the GPU die. Capacity sets the largest model a node can hold.
2. 02
   Tensor cores

   Matrix maths at low precision (FP8, FP4)Storing each number in eight or four bits instead of the sixteen or thirty-two a scientific calculation would use. AI models tolerate the loss of accuracy, and the payoff is large: fewer bits means less memory used and less data moved, which is the constraint that actually binds.. Rarely the binding constraint at frontier scale.
3. 03
   Scale-up: NVLink

   Chips inside a rack share memory coherently. This is where a model larger than one GPU actually lives.
4. 04
   Scale-out: Ethernet / InfiniBand

   Racks are joined into clusters. Congestion here, not FLOPs, sets real training throughput.
5. 05
   Software schedules it

   CUDA, cuDNN, TensorRT, Dynamo decide what runs where. The efficiency delta between good and poor scheduling is large.

Figure 2 · Evidence: NVIDIA FY2026 10-K, Item 1 (technology stack description); NVIDIA CFO Commentary Q1 FY2027 (InfiniBand, Spectrum-X and NVLink cited as joint demand drivers); NVIDIA GB200 multi-node tuning guide (NVLink domain expansion from eight GPUs to 72). Method: Sequence describes the standard data path for transformer inference; no vendor-specific performance claim is made. Synthesis: Steps 03 and 04 are where NVIDIA's differentiation is hardest to replicate, and steps 01 and 02 are where it is easiest.

Two of those steps deserve their names in the prose, because the rest of this report is ordered by them. Scale-up is what happens inside a single rack: a few dozen chips joined so tightly that they behave as one machine with one pool of memory. Scale-out is what happens between racks: many of those machines joined into a cluster by a more conventional network. Inside the box, and between boxes. The distinction sounds mechanical and is not — they are different engineering problems solved by different suppliers, and the moat map later in this brief is built on the difference.

Step 02 is the matchable one. Building a good matrix engine is now well-understood engineering, which is precisely why Google, Amazon, Microsoft, Meta and Broadcom have all done it. Matching steps 03 and 04 is a different order of problem: switch silicon, cabling, thermals, power delivery and a manufacturing chain that arrives as one product. That is a systems problem, and systems problems are where incumbency compounds.

03
The CUDA estate — what it is, and what it is not

NVIDIA discloses "over 7.5 million developers worldwide using CUDA and our other software tools," support for 6,000 applications, and that its platforms power "over 78% of the supercomputers on the global TOP500 list." More than half of NVIDIA's engineers work on software. Cumulative research and development since inception is $76.7 billion (all: FY2026 10-K, Item 1).

The switching-cost mechanic is real but frequently mis-stated. It does not operate at the level of the frontier lab. A lab with a thousand engineers writing custom kernels can and does port to alternative silicon; Anthropic states plainly that it runs Claude on "AWS Trainium, Google TPUs, and NVIDIA GPUs" and matches "workloads to the chips best suited for them" (Anthropic, 6 April 2026). The lock-in operates on the long tail: the enterprise with four engineers, the biotech using a domain library, the ISVIndependent software vendor — a company that sells software designed to run on somebody else's hardware. An ISV cannot choose its customers' chips, so it writes for whatever is already installed, which is what makes an installed base sticky long after the technical case for it has gone. shipping a product that must run on whatever the customer already owns. That tail is enormous and sticky. It is also — and this is what matters for the equity — not where the incremental dollar of data-centre revenue comes from.

CUDA is a superb defence of the installed base and a weak defence of the marginal frontier order. PyTorch's own installation path supports ROCm, PyTorch Monarch was ported to AMD Instinct GPUs with ROCm and passed its upstreamed test suite, and AMD publishes current vLLM guidance for MI300X, MI325X, MI350X and MI355X GPUs (PyTorch docs, retrieved 11 Aug 2026; PyTorch Foundation, 6 Jul 2026; AMD ROCm vLLM docs, 29 May 2026). OpenAI TritonAn open-source language for writing the low-level routines that run on an accelerator, designed so that one piece of code can be compiled for more than one vendor's chip. It exists precisely to spare developers from hand-writing those routines separately for each hardware maker. has an AMD ROCm install path, and MLIRA shared toolkit for building compilers. Its value here is that several hardware vendors can plug into the same machinery, so a program can be described once and then translated down to whichever chip is present — the mechanism by which a proprietary software layer stops being the only road.'s GPU dialect is explicitly designed to lower GPU work toward target backends including NVVM and ROCDL — in plain terms, to translate one description of a calculation into the machine-level form that either an NVIDIA or an AMD chip can actually execute (AMD ROCm Triton install docs, retrieved 11 Aug 2026; MLIR GPU dialect docs, retrieved 11 Aug 2026; MLIR AMDGPU dialect docs, retrieved 11 Aug 2026). What ROCm still cannot do is automatically translate the CUDA library calls — cuDNN, cuBLAS, TensorRT — that carry NVIDIA's accumulated optimisation. The distinction that decides this is between two ways of asking a chip to do something. A framework call is written once, in PyTorch or a layer like it, and the framework works out how to run it on whatever hardware is present; it travels. A kernel is the low-level routine that actually executes on the chip — frequently hand-written and tuned for one architecture's particular quirks — and it does not travel, because the quirks are not the same on the next chip. Porting is therefore easy at one level and brutal at the other, and which level a buyer lives at determines whether CUDA holds them. Portability is close where the workload is a framework call, and remains distant where it is a hand-tuned kernel. Observed docs; no parity benchmark used

A moat that protects the customers you already have, while the new customers write in PyTorch, is a moat around a shrinking castle.

On the limits of the software estate

04
The silicon cadence, and what an annual cycle actually buys

NVIDIA moved from a roughly two-year architecture cadence to an annual one. Blackwell launched in 2024; Blackwell Ultra "launched and scaled" through FY2026; Blackwell 300 products drove the April 2026 quarter; Vera Rubin entered full production announcement on 31 May 2026 with production shipments beginning in autumn 2026. Rubin Ultra and Feynman sit further out on the published roadmap.

The strategic function of the annual cadence is widely misread as "staying ahead on performance." It does something more useful than that. A one-year cycle means a competitor's product is obsolete against the incumbent's next part by the time it reaches volume — which is exactly what happens to a custom accelerator with an 18-to-30-month design cycle. It also compresses the window in which a buyer can amortise an alternative. AMD's MI450-series first gigawatt for OpenAI is scheduled for the second half of 2026, against a Vera Rubin ramp beginning in the same window. Note the unit, because it recurs throughout this brief. Deals of this size are now quoted in gigawatts of electrical power rather than in chips or in dollars — a gigawatt being roughly the output of a large power station — because what limits how much compute actually gets installed is how much power a site can draw and when the grid can deliver it. The industry has started denominating its contracts in the thing that is genuinely scarce. The cadence does not have to win a benchmark. It has to make the alternative's payback arithmetic uncomfortable.

But cadence is a lead, not an annuity. It is bought, every year, with roughly $6.3 billion a quarter of research and development (Q1 FY2027, up 52% year on year in total operating expense) and with foundry and packaging capacity that must be reserved years ahead. It persists only while NVIDIA can outspend and out-schedule. Broadcom, whose customers now fund the design directly, reported $10.8 billion of AI semiconductor revenue in the quarter ended 3 May 2026 and guided the next quarter to $16.0 billion, “over 200 percent year-over-year” (Broadcom Q2 FY2026 results, 3 June 2026) — a scale at which it can afford the same rhythm.

Evidence: NVIDIA Form 10-Q for the quarter ended 26 Apr 2026 (MD&A); CFO Commentary Q1 FY2027; NVIDIA FY2026 10-K Item 1; NVIDIA newsroom release of 31 May 2026; NVIDIA GB200 NVL72 product page. Method: Only status statements made by the issuer are reproduced; no third-party performance benchmark is used. Synthesis: The disclosed sequence shows the product widening — from chip, to rack, to a five-rack complex that now contains licensed third-party inference silicon.

05
The rack as the unit of compute

Somewhere between Hopper and Blackwell, NVIDIA stopped selling a component into someone else's design and started selling the design.

A GB200 NVL72 rack is one coherent machine: 72 GPUs joined by NVLink through NVSwitchNVIDIA's switch chip for NVLink — the part that lets every GPU in the rack talk to every other one directly, instead of passing messages along a chain. It is the piece of silicon that makes a coherent domain of seventy-two chips possible at all, and no competitor ships an equivalent in production today. silicon so that software addresses them, for many purposes, as a single very large accelerator with a single very large pool of memory; NVIDIA's product page identifies 36 Grace CPUs, 72 Blackwell GPUs, a 72-GPU NVLink domain and 130 TB/s of NVLink Switch bandwidth (NVIDIA GB200 NVL72 product page, retrieved 11 Aug 2026). This is not a marketing distinction. Coherent is the load-bearing word: it means the chips share one address space, so any of them can read what another has just written without a programmer copying data by hand, and a model far too large for one accelerator can be spread across all seventy-two and still be treated as though it lived on one. A domain is simply how many chips that trick extends to. Getting seventy-two to behave that way is a systems problem — switches, cabling, timing, thermals — rather than a chip problem, which is why it has proved so much harder to copy than the chip. A model that does not fit in one GPU's HBM must be shardedSplit into pieces spread across several chips, each holding part of the model. Every boundary between pieces is a point where data has to cross a wire instead of staying put, so the fewer boundaries a model has to cross, the faster and cheaper it runs., and every shard boundary costs latencyDelay — the time between asking for something and getting it. In this context it is the wait while data travels between chips, and it is what a user experiences as a slow answer.; widening the coherent domain from eight GPUs to seventy-two moves the boundary out far enough that a frontier-scale mixture-of-expertsA model design in which only a fraction of the network — the "experts" relevant to the input — is used for each token, rather than the whole thing. It buys enormous size at modest running cost, but it also means tokens are constantly being routed between chips, which turns the interconnect into the bottleneck. model can be served without crossing it on every token.

The second-order consequences matter more than the performance claim.

It changes who bears integration risk. When NVIDIA shipped boards, the ODM (original design manufacturer — the contract firm that actually builds the servers) and the customer owned the thermal, power and validation problem. When NVIDIA ships a rack reference designA complete blueprint for a machine — layout, power, cooling, cabling, validated components — that the designer hands to contract manufacturers to build. Whoever writes the reference design decides what goes in the box, and the ecosystem of factories trained to build it becomes an asset that cannot be bought in one product cycle., NVIDIA owns it — and captures the value of owning it. The company's own warranty accrual tells the story: product warranty liabilities rose from $1.29 billion at the start of FY2026 to $2.95 billion at 26 April 2026, "primarily related to our Compute & Networking segment." Rack-scale is a higher-margin, higher-obligation business.

It raises the switching cost above the chip level. A buyer who has built a data hall around a liquid-cooled 72-GPU rack with NVIDIA's power and cooling envelope cannot swap in an alternative accelerator without re-engineering the hall. That is a facility-level lock-in with a much longer half-life than a software one.

It converts manufacturability into a moat. NVIDIA describes "hundreds of NVIDIA supply chain ecosystem partners — 150 in Taiwan alone — across 350+ factories and 30 countries," and the Vera Rubin launch names Dell, HPE, Lenovo, Supermicro, ASUS, Foxconn, GIGABYTE, Pegatron, Quanta, Wistron and Wiwynn as builders (NVIDIA, 31 May 2026). Issuer claim No competitor has an equivalent ecosystem trained on its rack, and a rack ecosystem is not something a rival buys in one product cycle.

06
Networking — the Mellanox inheritance, and the number nobody quotes

NVIDIA's Data Center business splits, under the presentation it used through FY2026, into compute and networking. For fiscal 2026 those were $162.4 billion and $31.4 billion respectively; networking was 16.2% of Data Center revenue (FY2026 10-K, revenue by end market). In the quarter ended 26 April 2026 the split was $60.4 billion and $14.8 billion — networking now 19.7% of Data Center, and growing at 199% year on year against compute's 77%.

Over one year, NVIDIA's networking business grew roughly two and a half times faster than its accelerator business, and it is now running at a $59 billion annualised rate. That single line — not the whole company, one line inside it — is larger than the entire data-centre revenue of AMD, and roughly six times Marvell's most recent quarterly revenue of $2.418 billion. Derived: $14.8bn × 4; scope note — annualising one quarter is a run-rate, not a forecast

The networking franchise runs on three products with different competitive positions. InfiniBandA networking standard that is not Ethernet, built for very low delay between machines and long used in supercomputing. NVIDIA acquired it with Mellanox; because almost nobody else sells it, choosing InfiniBand is close to choosing NVIDIA., inherited from Mellanox, remains dominant for the most latency-sensitive training clusters and is effectively a single-vendor market. Spectrum-X is NVIDIA's AI-tuned Ethernet, and it is the strategically important one: Ethernet is an open standard where Broadcom, Arista and Cisco all compete, and NVIDIA's answer has been to win anyway on congestion controlThe logic that decides what happens when too much data wants the same path at once. In an ordinary network congestion means a slow web page; in a training cluster where thousands of chips must finish a step together, one congested link stalls all of them, so handling congestion well is worth a large fraction of the machine's real throughput. and end-to-end tuning — Meta and Oracle have both selected it, NVIDIA claiming 95% data-throughput efficiency against roughly 60% for off-the-shelf Ethernet (NVIDIA, 13 October 2025). NVLink, the in-rack scale-up fabric, is the one with no substitute in production today.

The right benchmark for the Ethernet half of this is Arista Networks, the strongest independent AI-networking franchise. Arista's total revenue in the quarter ended 30 June 2026 was $3.036 billion, on which it earned $1.910 billion of gross profit — a 62.9% gross margin — with 26% and 16% of 2025 revenue coming from two end customers (Arista Form 10-Q, quarter ended 30 June 2026). Derived: 1,910.3 ÷ 3,035.7 = 62.9% Against NVIDIA's $14.8 billion networking quarter, the shape of the market is plain: the best pure-play competitor earns roughly a fifth of NVIDIA's networking revenue at twelve points less gross margin, while carrying the same customer-concentration problem. Ethernet being an open standard has not, so far, produced an open-standard margin.

The competitive response is UALinkUltra Accelerator Link — an open industry standard for joining accelerators inside a rack, backed by a consortium of NVIDIA's competitors. It is the attempt to make scale-up a commodity the way Ethernet made scale-out one; whether it works is one of the report's live questions., an open scale-up standard. The consortium says the UALink 200G 1.0 specification is available now, defines a low-latency, high-bandwidth interconnect between accelerators and switches in AI podsA vendor's term for a block of racks wired and sold as one unit of compute — the building block a data centre is filled with, rather than an individual server., and enables scale-up connection for up to 1,024 accelerators (UALink specification page, retrieved 11 Aug 2026; UALink About page, retrieved 11 Aug 2026). AMD confirms that its Helios rack-scale system and MI400 series entered full production with shipments beginning late in its third quarter of 2026 (AMD, 4 August 2026). That is the correct competitive answer, and it arrives roughly two product generations after NVLink. Specification availability is observed; production adoption remains unverified

07
The software above CUDA

Below the frameworks and above the metal sits the layer that most analyses skip: cuDNN and cuBLASNVIDIA's libraries of ready-made building blocks — the standard mathematical operations every AI model needs, written and tuned by NVIDIA so that nobody else has to. Fifteen years of that tuning is the part of CUDA a rival cannot simply reimplement over a weekend. (the primitive libraries), TensorRTNVIDIA software that takes a finished, trained model and reworks it to run as fast as possible on NVIDIA hardware before it is put into service — trimming precision, fusing steps, choosing routines. The gain is free performance for the customer and none of it transfers to another vendor's chip. and TensorRT-LLM (inference compilation), the CUDA-X collection, NIM microservicesPre-packaged model-serving components NVIDIA ships so an enterprise can deploy a model without building the plumbing itself. Convenience software, sold as part of the platform rather than as a business in its own right., and — new this cycle — Dynamo, the inference scheduler NVIDIA says "delivers a significant increase in token throughput and reduction in cost per token compared to the Hopper generation." Dynamo 1.0 entered production alongside the Q1 FY2027 quarter.

A software layer that raises tokens per second per rack does not merely make the hardware faster; it lowers the customer's cost per token while leaving NVIDIA's price per rack untouched. NVIDIA can improve its customer's unit economics without giving up price. That is the cleanest form of pricing power available to a hardware company, and it is why gross margin has held near 75% through a generational transition that should, mechanically, have compressed it — a full-rack system carries far more bought-in content (memory, power, cooling, cabling) than a board did.

NVIDIA also releases open model platforms — Nemotron for agentic AI, Cosmos for physical AI — described in the 10-K as being "in support of market development." Read that as demand generation, not as a product line. Free models that run best on NVIDIA racks are a subsidy to the installed base, funded from gross margin, in the same spirit as CUDA in 2006.

08
Systems, the channel, and where the revenue is actually booked

NVIDIA sells to "direct customers" — add-in board makers, distributors, ODMs, OEMsOriginal equipment manufacturers — firms such as Dell or HPE that sell finished, branded servers to end customers, as distinct from the ODMs that build machines to someone else's design without putting their own name on them., cloud service providers, AI model makers and system integrators — and its products reach "indirect customers," which the company defines to include CSPs, neocloudA new class of company whose entire business is renting out GPUs — CoreWeave is the largest — typically financed with debt secured against the chips themselves. They buy nothing but NVIDIA, which makes them NVIDIA's most loyal customers and its most fragile ones. builders, AI model makers, enterprises and public-sector entities (FY2026 10-K, concentration of revenue). This two-layer structure is why the geographic and customer disclosures are so easily misread. Taiwan was $12.0 billion of Q1 FY2027 revenue on a customer-headquarters basis, but NVIDIA estimates that in FY2026 "76% of Data Center revenue from Taiwan-headquartered customers was attributed to end customers based in the United States and Europe." The ODM books it; an American hyperscalerOne of the handful of firms — Amazon, Microsoft, Google, Meta — that run data centres at global scale for their own services and for rent. They are simultaneously NVIDIA's largest customers and the only buyers with the money and the engineering depth to design their way out of buying from it. consumes it.

The FY2026 10-K says this: "We estimate that one AI research and deployment company contributed to a meaningful amount of our revenue purchasing cloud services from our customers in fiscal year 2026." NVIDIA is telling shareholders that a single model lab — buying compute from NVIDIA's customers rather than from NVIDIA — was a material driver of NVIDIA's own revenue. That is a disclosed dependency that appears nowhere in the customer-concentration table, and it is the formal basis for the circularity discussion in Part II.

09
Foundry and packaging — the physical chokepoint

NVIDIA designs; it does not manufacture. Every leading-edge accelerator on earth — NVIDIA's, AMD's, Google's TPU, Amazon's Trainium, Microsoft's Maia, Meta's MTIA, and Broadcom's custom XPUsA catch-all for accelerators that are neither ordinary CPUs nor off-the-shelf GPUs — in Broadcom's usage, custom AI chips designed to a single customer's specification and built for that customer alone. — is fabricated by TSMC and packaged using TSMC's CoWoS (chip-on-wafer-on-substrate: the technique that places logic dieThe piece of silicon that does the computing, as opposed to the memory stacked beside it. A "die" is a single chip cut from a wafer; modern accelerators are several dies packaged together and sold as one part. and stacked memory on a common interposerA thin slab of silicon that sits underneath two or more chips and carries the wiring between them. It lets memory and logic communicate almost as if they were one chip, which is why packaging — not just chipmaking — became a bottleneck for the whole industry. so they can talk at memory speed).

TSMC reported second-quarter 2026 revenue of $40.20 billion, up 33.7% year on year, with a 67.7% gross margin and 60.3% operating margin; advanced technologies (7nm and belowA shorthand for how fine a manufacturing process is — the "process node." Smaller numbers mean more transistors in the same area and less power per calculation; they no longer correspond to any physical measurement, but the ranking is real and only a few plants in the world can do the smallest ones. Note that node is also used elsewhere in this report to mean a single server, a different thing entirely.) were 77% of waferThe polished disc of silicon that chips are printed on, hundreds at a time, before being cut apart. Foundry capacity is measured in wafers, which is why "wafer revenue" is the natural unit for TSMC's business. revenue, with 3nm at 30% and 2nm at 3% (TSMC Q2 2026 results, filed on Form 6-K, 16 July 2026). Third-quarter guidance is $44.6–45.8 billion.

TSMC's own annual report gives an unusually direct read on how the AI cycle has redistributed its customer base. Its ten largest customers were 70%, 76% and 78% of net revenue in 2023, 2024 and 2025; its largest customer fell from 25% to 22% to 19%, while its second-largest rose from 11% to 12% to 17% (TSMC Form 20-F for FY2025, filed 16 April 2026). TSMC does not name customers, so the identification is an inference — but a second customer rising from a ninth to a sixth of the world's leading-edge foundry inside two years is a scale of change only the AI accelerator business can account for. Inference — TSMC does not identify its customers; the disclosed percentages are facts, the attribution is not

Who controls this node? A single company, on a single island, with a duopoly-free position at the leading edge. How durable? Extremely — Intel Foundry and Samsung have not qualifiedIndustry usage: formally approved by the buyer for production after testing — not a description of the part's quality but of its status. A component that is not qualified cannot be shipped in a customer's machine however good it is, which is why qualification timing, rather than technical merit, often decides who supplies a generation. a competitive leading-edge AI part at volume. Can it be replicated? Only with a decade and a hundred billion dollars, which is roughly what TSMC's own Arizona expansion represents. And critically: what happens to NVIDIA's rent if this node doubles?

The answer is uncomfortable, and it is why the supply constraint is not simply a friend. CoWoS capacity roughly doubled through 2025 and is expanding again through 2026. Estimated — third-party capacity tracking, not TSMC-disclosed Every increment of packaging capacity that comes online is capacity available to everyone designing an accelerator, not to NVIDIA alone. Scarcity at the packaging node has been suppressing competitor volumes at least as much as it has been suppressing NVIDIA's. Relieving it is a competitive event, not a purely favourable one.

1. 01
   Leading-edge wafer

   TSMC N3/N2. Single credible supplier; 77% of TSMC wafer revenue is now 7nm and below.
2. 02
   HBM stack

   SK hynix, Samsung, Micron. HBM4 entered mass shipment in Q2 2026. Structurally short.
3. 03
   CoWoS packaging

   Logic and memory joined on an interposer. The binding physical constraint for the whole industry, not just NVIDIA.
4. 04
   Rack integration

   Foxconn, Quanta, Wistron, Dell, HPE, Supermicro. NVIDIA supplies the reference design and the switch silicon.
5. 05
   Power and the hall

   Grid interconnection now the practical gate. NVIDIA names data centres, energy and capital as risks to its own revenue.

Figure 5 · Evidence: TSMC 2Q26 results (Form 6-K, 16 Jul 2026); SK hynix 2Q26 results (29 Jul 2026); Samsung HBM4 mass-production release (12 Feb 2026); NVIDIA Q1 FY2027 10-Q, MD&A and Item 1A; NVIDIA press release 31 May 2026 (partner list). Method: Sequence as disclosed by the named issuers; no throughput or yield figure is asserted. Synthesis: Steps 01–03 are shared by every accelerator vendor, so relieving them helps competitors at least as much as NVIDIA; step 04 is where NVIDIA's specific advantage sits.

10
The memory oligopoly — the most changed fact in the chain

The DRAM industry spent forty years destroying its own returns. In eighteen months it stopped, and the mechanism it used should worry every buyer of AI hardware — including NVIDIA.

Micron's third fiscal quarter of 2026, ended 28 May 2026, produced $41.46 billion of revenue and $35.06 billion of gross profit: an 84.6% gross margin, against 38% in the year-ago quarter (Micron Form 10-Q, filed 25 June 2026). SK hynix reported second-quarter 2026 revenue of KRW 79.32 trillion and operating profit of KRW 60.54 trillion — a 76.3% operating margin — and said it had "finalized Long-Term Agreements (LTAs) with around 10 customers" (SK hynix, 29 July 2026). Samsung, having lagged on HBM3E qualification, said on 12 February 2026 that it had begun HBM4 mass production and shipped commercial products, with HBM4E samples expected in the second half of 2026 and custom HBM samples in 2027 (Samsung Global Newsroom, 12 Feb 2026). It also announced HBM4 alignment with AMD's MI455X and Helios roadmap and a July 2026 memory/foundry MOU with Broadcom (Samsung/AMD, 18 Mar 2026; Samsung/Broadcom, 25 Jul 2026). NVIDIA qualification is not disclosed

The mechanism matters more than the margin, and it is worth stating plainly before the quotations arrive. A take-or-pay contract binds the buyer rather than the seller: the buyer commits to a volume and pays for it whether or not it takes delivery. A floor price sets the least the seller can be paid per unit for the term. Put the two together and the seller has removed both of the ways a downturn normally hurts it — the volume cannot be walked away from and the price cannot fall through the floor. Whoever signs the other side of that contract has taken both risks onto itself. Micron describes its strategic customer agreements as "take-or-pay agreements, with binding commitments for specific volumes over the multi-year contract terms," where "the largest agreements generally have a ceiling price for existing products that approximates the market price in the second calendar quarter of 2026, and a floor price through the term of the agreement." It then states that it expects gross margins from these agreements, "even at floor pricing levels, to yield gross margins well above our peak quarterly margins in any past cycle."

A memory manufacturer has just told the market that its worst contracted case is better than its best historical case. Whoever is on the other side of those contracts has agreed to a floor. And the largest single buyer of HBM in the world is NVIDIA.

The layer below tells the same story from the opposite end. Super Micro — a company whose business is essentially building and shipping GPU racks — earned a 9.9% gross margin in the quarter ended 31 March 2026 on net sales up 122.7%, and reported a 3.4-point nine-month gross-margin decline "due to a change in product and customer mix, higher production and expedite costs as we began to ship new AI GPU platforms on a large scale" plus tariffs and inventory write-downs (Super Micro Form 10-Q, quarter ended 31 March 2026). Doubling revenue bought it nothing in margin. That is what a layer without a scarce right looks like, and it is the control experiment against which NVIDIA's 74.9% should be read.

The counter-argument is fair. NVIDIA's own gross margin expanded through this period, from an underlying ~71% in FY2026 to 74.9%, so it has evidently passed higher memory costs through. Correct — and that is a genuine demonstration of pricing power while demand exceeds supply. The asymmetry only bites in the other state of the world. Memory prices are contracted with floors; NVIDIA's prices are set on cancellable purchase orders. If end demand softens, NVIDIA's cost of goods is contractually defended and its revenue is not.

11
Who actually buys — and how concentrated it has become

In fiscal 2026, one direct customer was 22% of NVIDIA's total revenue and another 14% — 36% between them. One quarter later, in the three months to 26 April 2026, three direct customers were 21%, 17% and 16%: 54% of revenue. Three customers also held 30%, 18% and 16% of accounts receivable (Q1 FY2027 Form 10-Q, Note 13 and Note 6). In FY2024, by contrast, the largest direct customer was 13%.

The buyer set breaks into four groups, and their incentives explain most of what happens next.

Figure 8 · Evidence: NVIDIA CFO Commentary Q1 FY2027 (Hyperscale ≈50% of Data Center revenue; ACIE the balance); FY2026 10-K concentration-of-revenue note (indirect customers defined to include CSPs, neocloud builders, AI model makers, enterprises and public-sector entities). Method: Incentives are report-authored inferences from disclosed behaviour, not issuer statements. Synthesis: Only the neocloud tier has an unambiguous incentive to stay all-NVIDIA — and it is the tier with the weakest balance sheet.

NVIDIA's own new reporting framework makes the split visible. Hyperscale was $37.9 billion of the April quarter and ACIE (AI Clouds, Industrial and Enterprise) $37.4 billion — almost exactly half each, with ACIE growing 74% and Hyperscale 115%. The company frames this as diversification. It is — but the faster-growing half is the one with the deepest pockets and the strongest incentive to design its way out.

12
The alternatives, and what each one gives up

A custom accelerator is a trade. It buys performance per dollar on a known workload and sells flexibility, ecosystem and resale value. Whether the trade is good depends almost entirely on whether the buyer's workload mix is stable enough to amortise an eighteen-month design cycle — which is why inference, where the workload is a fixed model serving a fixed pattern, is the natural beachhead, and frontier training is not.

That trade has a name, and the name explains the fear. A general-purpose GPU is built to run whatever arrives — including a model architecture nobody has invented yet — and pays for that flexibility in silicon area and power. An ASIC, an application-specific integrated circuit, is the opposite: hard-wired for one job, so it does that job faster and on far less power, and cannot be repurposed when the job changes. The whole custom-silicon debate reduces to one wager: that the workload will hold still long enough for the fixed chip to earn back its design cost.

A second distinction organises everything that follows, and the report leans on it heavily. A merchant supplier sells its chips to anyone who will buy them. A captive programme builds them only for its owner's own data centres. The difference is not about volume, it is about price: a captive chip quietly removes demand from NVIDIA, while a merchant chip competes for the same order and can force NVIDIA to quote against it. Which of the two a programme is turns out to matter more than how good its silicon is.

Google TPU (v7 "Ironwood"). The most complete alternative in existence, and the only one with its own scale-up interconnect, its own compiler path (JAX and PyTorch/XLA)The route from code a researcher writes down to instructions a chip executes. JAX is Google's own framework; XLA is the compiler that translates JAX or PyTorch into TPU instructions. Owning this route means Google never has to ask NVIDIA's software estate for permission — the reason its chips are usable where other in-house efforts stall., and a frontier model to prove it. Anthropic's April 2026 announcement with Google and Broadcom covers "multiple gigawatts of next-generation TPU capacity that we expect to come online starting in 2027," with "the vast majority of the new compute" sited in the United States (Anthropic, 6 April 2026). The decisive change is in Alphabet's own 10-Q: Google Cloud now "generates product revenues primarily from the sale of TPU systems," and Alphabet has "signed a limited number of agreements to supply TPU systems to customers who require or provide on-premises infrastructure," beginning to recognise revenue in Q2 2026 "with the significant majority to be recognized in 2027" (Alphabet Form 10-Q, quarter ended 30 June 2026). Google Cloud revenue grew 81.8% to $24.77 billion with operating income of $8.81 billion.

Broadcom custom XPUs. Not a chip company competing with NVIDIA so much as an arms dealer to everyone who wants to leave. AI semiconductor revenue was $10.8 billion in the quarter ended 3 May 2026, up 143% year on year, with the following quarter guided to $16.0 billion; its Form 10-Q discloses approximately $164.6 billion of firmly committed remaining performance obligations, "includ[ing] obligations under a long-term contract for custom AI accelerators entered in the fiscal quarter ended May 3, 2026." That contract is widely reported as OpenAI's. Customer not named in the filing

AWS Trainium. Trainium3 UltraServersAmazon's name for a block of its own accelerators wired together and rented as a single unit — its equivalent of NVIDIA's rack, and the sign that Amazon too has stopped selling compute by the chip. are generally available, claimed at "up to 4.4x more compute performance" and "almost 4x more memory bandwidth" than Trainium2, with Anthropic named among customers. The strategically revealing detail is Trainium4, which AWS says is being designed to support "NVIDIA NVLink Fusion high-speed chip interconnect technology" (AWS, Trainium3 UltraServers; NVIDIA technical blog, 2 Dec 2025). Amazon has chosen interoperability over independence.

AMD Instinct. Data Center revenue of $6.718 billion in the June 2026 quarter, up 107%, with the MI400 series and the Helios rack-scale system in full production and shipping from late Q3 (AMD, 4 August 2026). OpenAI has contracted for 6 gigawatts across multiple Instinct generations — the first gigawatt of MI450 starting in the second half of 2026 — against a warrant for up to 160 million AMD shares vesting on deployment, share-price and commercial milestones (AMD, 6 October 2025); AMD's Q2 2026 release adds partnerships “deploying up to 2 gigawatts of MI450 Series GPUs.” AMD's constraint is not design — it is that its consolidated gross margin of 54% leaves far less room to fund the annual cadence than NVIDIA's 75%.

Microsoft Maia and Meta MTIA. Both are first-party programmes with no merchant ambition disclosed. Microsoft describes Maia 100 as its first in-house AI accelerator, co-designed from silicon to software to systems for Azure AI infrastructure, and its January 2026 Maia 200 release likewise frames the part as an inference accelerator integrated into Microsoft Azure rather than as a merchant product (Microsoft Azure Blog, 3 Apr 2024; Microsoft Source EMEA, 26 Jan 2026). Meta announced in March 2026 that it is "developing and deploying four new generations of MTIA chips within the next two years," with MTIA 300 already in production for ranking and recommendations training and MTIA 400/450/500 aimed primarily at generative-AI inference; it already deploys "hundreds of thousands of MTIA chips for inference" (Meta, 11 March 2026). Meta frames this as "a portfolio approach… while keeping our own MTIA custom silicon at the center." The phrasing concedes what it must and no more: custom silicon at the centre, merchant GPUs still in the portfolio.

13
The rulebook — what an export licence actually permits

The China position has moved three times in fifteen months, and the current state is more permissive on paper and more restrictive in practice than most summaries suggest.

In April 2025 the US government required a licence for exports to China and D:5 countriesA grouping in the US export-control rules covering countries of national-security concern — the list to which the tightest restrictions on advanced computing chips apply. of the H20 and any circuit matching its memory or interconnect bandwidth; NVIDIA took a $4.5 billion charge for excess H20 inventory and purchase obligations. In August 2025 licences were granted and NVIDIA "generated approximately $60 million in H20 revenue under those licenses," while noting that US officials "expressed an expectation that the USG will receive 15% or more of the revenue generated from licensed sales… but the USG did not publish a regulation codifying such requirement." In February 2026 a licence was granted for small volumes of H200 to specific China-based customers; as of the FY2026 10-K, "we have not generated any revenue under the H200 licensing program, and do not yet know whether any imports will be allowed into China," and any H200 shipped under it faces "a 25% tariff upon importation into the United States" because of a mandatory US inspection step.

The regulatory anchor is a BISThe Bureau of Industry and Security, the arm of the US Commerce Department that writes and administers export-control rules and decides who gets a licence to ship advanced chips abroad. final rule published 15 January 2026, effective the same day, which changed the licence review policy for the H200 "and its equivalents, as well as less advanced chips" from a presumption of denial to case-by-case review — conditional on certifications that domestic supply is sufficient, that production for China "will not divert global foundry capacity" from US end users, that the recipient has adequate security procedures, and that the item passes independent third-party testing in the United States (Federal Register 91 FR, doc. 2026-00789).

"Will not divert global foundry capacity" makes China sales contingent on there being slack at TSMC — which, while CoWoS is the binding constraint, there is not. The rule therefore grants an option that cannot be exercised at scale precisely when it would be most valuable. That is not an accident of drafting; it is the policy.

A mirror-image risk gets less attention. NVIDIA's own risk factors warn that export controls "may increase investment in foreign competitors, which would be less likely to be restricted by U.S. controls," and that an agency of the Chinese government "announced an Action Plan that endorses new standards regarding the compute performance per watt and per memory bandwidth of accelerators used in new and renovated data centers in China" — standards NVIDIA says could be set so that it cannot design to them even if controls were lifted. The market NVIDIA has lost may not be recoverable on any policy path.

14
Reading the numbers — the traps in NVIDIA's own disclosure

Three things about the presentation have to be held straight before any Part II claim is tested.

The segments were re-cut. From Q1 FY2027 NVIDIA reports two market platforms — Data Center (split into Hyperscale and ACIE) and Edge Computing — replacing the old Data Center / Gaming / ProViz / Automotive end-market presentation. Gaming, workstations, robotics and automotive are now inside "Edge Computing," which was $6.37 billion in the April quarter. The two reportable segments for accounting purposes remain Compute & Networking ($74.55 billion) and Graphics ($7.07 billion). Any comparison across the boundary needs the recast figures, which NVIDIA provided.

Net income now contains a large non-operating component. Q1 FY2027 net income was $58.3 billion on operating income of $53.5 billion. The difference is chiefly $15.9 billion of net gains on equity securities — $13.4 billion unrealised on publicly held stocks and $2.6 billion on private ones. Excluding those gains net of tax, net margin was approximately 55.2% rather than the headline 71.5%. Derived: (58,321 − 15,936 × (1 − 16.6%)) ÷ 81,615 NVIDIA's non-GAAP measures exclude these gains; its GAAP EPS of $2.39 against non-GAAP $1.87 is almost entirely this item. A hypothetical 10% fall in the public-equity portfolio would cut its value by $3.9 billion.

The balance sheet has changed character. Goodwill went from $6.26 billion at 25 October 2025 to $20.89 billion at 26 April 2026, almost entirely the $14.4 billion booked on the Groq licence. Inventory reached $25.8 billion. Supply and capacity commitments reached $119 billion. This is no longer the balance sheet of a fabless designer.

15
Conclusion first

Structural view: hold the franchise, but underwrite the rack — not the chip, and not the multiple. NVIDIA's excess return is durable where it is systemic and contestable where it is silicon; the equity is priced for duration, and duration is exactly what memory contracts, customer concentration and merchant TPUs put at risk.

The verdict: a structural HOLD with a constructive bias, conditional on gross margin. Not a buy, because the price already pays for the demonstrated fact pattern and the marginal buyer is now underwriting an assumption about 2029 rather than an observation about 2026. Not an avoid, because the moat is real, is in the least-copied part of the stack, and is being widened by the very forces the bears cite. Two conditions convert it to a buy and three convert it to an avoid; both sets are stated in section 31 with dates attached.

What is contracted or disclosed today, as against hoped for:

Evidence: as cited per row. Method: Rows are sorted by the strength of the commitment, from issuer guidance and contractual obligations through to non-binding letters of intent. Synthesis: The asymmetry is the point — NVIDIA's obligations to its suppliers are contractual and dated; its customers' obligations to NVIDIA largely are not. Backlog language in the press does not correspond to any disclosed remaining-performance-obligation figure, unlike at Broadcom, Microsoft or Alphabet.

That table frames everything that follows. Broadcom discloses $164.6 billion of firmly committed remaining performance obligations. Microsoft discloses $678 billion of commercial RPO, up 84%. Alphabet discloses $513.9 billion of Google Cloud backlog. NVIDIA discloses none, because its business genuinely does not work that way — and that is a real informational disadvantage for anyone trying to underwrite its duration.

16
What consensus prices, and where it is incomplete

The prevailing view is not wrong so much as one layer too shallow. It holds that (a) AI capex compounds for years, (b) CUDA locks customers in, (c) custom ASICs nibble at inference but cannot touch training, and therefore (d) NVIDIA compounds with the market at a ~75% gross margin. Each leg is defensible. Together they add up to a conclusion about the wrong variable.

Figure 14 · Evidence: NVIDIA FY2026 10-K Item 1 (7.5m developers); CFO Commentary Q1 FY2027 (networking +199% y/y, compute +77% y/y); Anthropic statement of 6 Apr 2026 on running across Trainium, TPU and NVIDIA GPUs. Method: Growth rates as reported by the issuer for the quarter ended 26 Apr 2026. Synthesis: Both propositions can be true; the revised one identifies which is binding on the marginal order.

Three further places where the consensus frame is incomplete.

First: the consensus underweights the buyer's balance sheet. Three direct customers now supply 54% of revenue. In every previous technology cycle, that degree of buyer concentration has eventually shown up in price, not in volume. It has not yet, because supply is short. It will, when it is not.

Second: the consensus treats memory as a cost line rather than as a counterparty. Micron's 84.6% gross margin and its take-or-pay floors are not a supply-chain footnote; they are a competing claim on the same end-customer dollar, and one that is now contractually senior to NVIDIA's.

Third: the consensus reads Google's TPU as an internal cost-saving programme. As of the June 2026 10-Q it is a product line with external, on-premises customers and recognised revenue. That reclassification changes what kind of competitor Alphabet is.

17
Moat durability, layer by layer — the heaviest section

One lens applies to every layer: who sets the price here, what happens to margin when a credible competitor, an in-house accelerator, an open software layer, added capacity or an export restriction arrives, and what dated evidence would prove the verdict wrong.

Defending a grade that sits against the thesis criterion. Layer 03 is graded durable-but-contested even though Spectrum-X competes on an open standard — which, by this report's own test, should imply commoditisation. The defence is specific: Ethernet is open, but the congestion-control behaviour of a 100,000-GPU training fabric is not a standards-body property, it is an end-to-end co-design property between NICNetwork interface card — the port through which a server plugs into the network. In an AI cluster the NIC does real work rather than just carrying traffic, which is why owning it, the switch and the software together is a different proposition from selling any one of them., switch and collective-communications libraryThe software that coordinates thousands of chips when they all have to combine their results — every accelerator finishing a step, pooling what it computed, and receiving the pooled answer before the next step starts. It is unglamorous and it is decisive: a training run moves at the speed of its slowest collective, so this library, the switch and the network card have to be tuned as one system. NVIDIA supplies all three., all three of which NVIDIA supplies. That is why Meta — a company with its own silicon programme, its own network engineering, and every incentive to buy merchant switches — selected Spectrum-X. Should Meta or Oracle publicly move a flagship AI fabric to a merchant Ethernet vendor, this grade falls to Contestable. That is the dated falsifier.

18
The interconnect thesis, and the consequence chain nobody follows

The fabric argument usually stops two steps short of its conclusion.

Step one. If the scale-up fabric is the binding constraint, then a rival's accelerator is only as good as the fabric it can be wired into. AMD's answer is UALink; Google's is its own ICIInter-Chip Interconnect — the proprietary links Google built to join its TPUs into a single large machine. It is Google's equivalent of NVLink, and the reason Google is the only rival that owns the whole stack rather than renting the hardest part of it.; Broadcom's customers use Ethernet. Amazon's answer, for Trainium4, is to support NVLink Fusion. That is not a concession forced by weakness — Amazon has 500,000 Trainium2 chips deployed and an anchor customer. It is a calculation that being inside NVIDIA's fabric is worth more than being outside it.

Step two. NVLink Fusion means NVIDIA earns on the deployment of a competitor's accelerator. Every gigawatt AWS builds with Trainium4 inside an NVLink-Fusion rack pulls NVIDIA switch silicon, NVIDIA CPUs or NICs, and NVIDIA's fabric licence. The custom-ASIC wave, which the consensus reads as pure share loss, is being partially converted into a networking annuity. Inference — the commercial terms of NVLink Fusion are not disclosed and the revenue contribution is not separately reported

Step three. Which moat strengthens precisely because the technology gets cheaper? Inference. As cost per token falls, token volume rises faster than price falls, and inference at scale is a networking-intensive workload once models exceed a single node — disaggregated prefill and decode, KV-cache movement, expert routing. Those three phrases carry the argument, so they are worth spelling out. Answering a prompt happens in two phases: reading the question, which the industry calls prefill, and writing the answer one token at a time, which it calls decode. The two want different things from a machine, so at scale they are split across different hardware — disaggregated — and the model's working memory of the conversation so far, the KV-cache, then has to be shipped from the machines that did the reading to the machines doing the writing. Expert routing adds a third stream of traffic: in a mixture-of-experts model each token is dispatched to a different specialised sub-network, so tokens are in constant motion between chips. Every one of those movements is a trip across the fabric rather than a calculation on a chip. Cheaper compute therefore increases, not decreases, the share of system value that sits in the fabric. This is the strongest structural argument for NVIDIA that does not depend on training demand at all, and it is why the Groq licence makes sense: buy the best inference architecture, put it in the rack, and let the fabric collect.

19
CUDA re-examined — the moat that is real and no longer binding

A software moat rarely dies by being replaced. It dies by being abstracted over. Nobody had to reimplement CUDA; PyTorch simply became the layer people write in, and PyTorch has backends. Triton compiles kernels for multiple targets. MLIR gives compiler writers a shared intermediate representationA halfway form between the code a person writes and the instructions a particular chip runs. Agree on the halfway form and any vendor can write the last stretch to their own hardware — which is precisely how a proprietary layer stops being the only road to the machine.. None of that removes NVIDIA's advantage — it relocates the advantage from "you must use CUDA" to "CUDA's libraries are faster," which is a performance argument and therefore a price argument.

The commercial translation: NVIDIA's software estate no longer prevents a switch; it sets the discount a competitor must offer to make one worthwhile. The sourced evidence now supports the mechanism, not a precise parity number: PyTorch supports ROCm as an installation target, PyTorch Monarch has been ported to AMD Instinct GPUs with ROCm, AMD publishes a current vLLM optimisation path for Instinct GPUs, Triton has an AMD ROCm install path, and MLIR supplies shared GPU abstractions (PyTorch docs, retrieved 11 Aug 2026; PyTorch Foundation, 6 Jul 2026; AMD ROCm vLLM docs, 29 May 2026; AMD ROCm Triton docs; MLIR GPU dialect docs). That evidence is enough to downgrade CUDA from absolute lock-in to switching cost; it is not enough to claim benchmark equivalence, and the report does not use benchmark equivalence as a conclusion.

AMD's problem is that it does not obviously have that headroom. Its consolidated gross margin was 54% against NVIDIA's 74.9%; if AMD prices twenty points below NVIDIA on equivalent performance it is not funding an annual cadence. Google's position is different in kind, because its TPU does not need to earn a merchant gross margin at all — it needs to lower Google's own cost per token, and any external sale is incremental. That asymmetry, not raw performance, is why Google is the more dangerous competitor.

20
Demand sustainability — the other heaviest section

The right question is not whether AI capex is a bubble. It is whether the buyers' funding sources outlast the buyers' enthusiasm — and on that, the disclosure is more reassuring than the commentary and more alarming than the price.

The buyers' own filings say what they have actually spent, on a calendar-aligned basis. In the first half of calendar 2026: Amazon $96.3 billion of cash capital expenditure, Alphabet $80.6 billion, Microsoft approximately $66.7 billion, Meta $50.9 billion. That is roughly $294 billion in six months from four companies, against roughly $190 billion in the same half of 2025.

Four things must be true for that spending to persist.

1. The buyers must be able to fund it. Increasingly they are not funding it purely from cash. Alphabet issued $20.0 billion of dollar notes and $31.8 billion of foreign-currency notes in the first half of 2026, plus $30.5 billion of net equity proceeds and $19.0 billion of mandatory convertible preferred stock, explicitly "for general corporate purposes, including capital expenditures to scale AI infrastructure and global compute," and carries $98.2 billion of long-term debt and $85.2 billion of leases not yet commenced. Meta raised $24.91 billion of net proceeds from senior notes in May 2026. AI capex has moved from a cash-flow item to a capital-markets item — the single most important change in the demand picture over the past year. Debt-funded demand is more fragile than cash-funded demand, and it is more sensitive to rates than to enthusiasm. Observed fact — issuer filings

2. The revenue must be arriving. It is, and it is arriving in the exact places the compute was pointed. Google Cloud revenue grew 81.8% year on year to $24.77 billion in Q2 2026 with operating income of $8.81 billion, up from $2.83 billion. AWS grew 36.8% to $42.23 billion. Microsoft Cloud revenue reached $214.4 billion for FY2026, up 27%, with Azure up 41% and commercial remaining performance obligations of $678 billion, up 84%. Alphabet's Google Cloud backlog is $513.9 billion. Over $1.19 trillion of contracted, unrecognised cloud revenue sits on two balance sheets. It is not proof that end demand is real, but it is a far stronger commitment structure than existed in any previous infrastructure bubble.

3. The unit economics must work at the model layer. Here the evidence is genuinely mixed and should not be overstated. Anthropic disclosed run-rate revenue "surpassed $30 billion — up from approximately $9 billion at the end of 2025," with more than 1,000 business customers spending over $1 million annually. That is a real, fast-compounding commercial business. Against it, credible reporting puts OpenAI's 2026 loss near $14 billion. Third-party estimate — OpenAI does not file The industry-level arithmetic frequently cited by bears — several hundred billion dollars of annual infrastructure spend against perhaps $50–60 billion of AI-specific revenue — is directionally informative and methodologically weak, since it compares a capital number to a revenue number and ignores the base businesses the compute also serves. It should not carry a conclusion, and here it does not.

4. The physical build must be possible. This is the constraint NVIDIA itself flags first. Its 10-Q states that "the availability of data centers, energy, and capital to support the buildout of NVIDIA AI infrastructure by our customers and partners is crucial," that "expanding energy capacity to meet demand is a complex, multi-year process," and that "access to capital can be particularly constrained for less-capitalized companies." When a supplier writes that its customers may not be able to find power or money, it is describing the shape of the eventual slowdown. Grid interconnection in major US markets is commonly quoted at 24–36 months. Estimated — industry reporting, not a regulator dataset

The trajectory of that contracted backlog is worth watching more closely than any single quarter's revenue. Alphabet's Google Cloud backlog went from $462.3 billion at 31 March 2026 to $513.9 billion at 30 June 2026 (Alphabet Form 10-Q, quarter ended 31 March 2026). Microsoft's total remaining performance obligation went from $633 billion at 31 March 2026 to $684 billion at 30 June 2026, with Azure growth accelerating from 40% to 41% (Microsoft Form 10-Q, quarter ended 31 March 2026). Backlog that is still building at roughly $50 billion a quarter, at two separate companies, is not the signature of a demand peak. Observed fact — issuer filings

5. The independent read-throughs. The most useful evidence about a supplier's demand is rarely the supplier's own commentary. Three counterparties, none of which reports to NVIDIA, published harder numbers than NVIDIA did — and two of them arrived within days of this brief's cutoff.

Evidence: TSMC July 2026 revenue report (Form 6-K, 10 Aug 2026); Oracle Form 10-K for FY ended 31 May 2026; Dell Form 10-Q for the quarter ended 1 May 2026. Method: All figures as reported by each issuer; TSMC's are in New Taiwan dollars and are not converted. Dell's growth of 8.6× is computed as 16,132 ÷ 1,882. Oracle's RPO covers all cloud and licence contracts, not AI alone, and Dell's AI-server revenue includes non-NVIDIA content — neither is a proxy for NVIDIA revenue. Synthesis: Three counterparties with no incentive to flatter NVIDIA, at three different points in the chain, independently corroborate that the build was still accelerating through July 2026. This is the strongest available answer to the digestion question, and it is worth more than any management assertion about order books.

Sell-in versus sell-through. The classic semiconductor failure mode is shipping into a channel that is not consuming. Three disclosed indicators argue against that today and one argues for caution. Days sales outstanding fell to 45 from 51 sequentially. NVIDIA's inventory rose to $25.8 billion but so did the supply commitments behind it — this is deliberate pre-positioning, and management says so. CoreWeave, the largest pure-play consumer of NVIDIA racks, reported $99.4 billion of revenue backlog and passed 1 GW of active power. The caution flag: inventory grew 21% sequentially against revenue growth of 20%, and provisions for inventory and excess purchase obligations still cost 1.2 points of gross margin in the quarter. Nothing here looks like 2018 crypto channel-stuffing. It also does not look like a company with no supply risk.

21
Concentration and circularity — the risk that is actually load-bearing

NVIDIA's three largest direct customers are 54% of revenue. NVIDIA holds $39 billion of publicly traded equities and recognised $15.9 billion of gains on its investment portfolio in a single quarter. Amazon invested $28.7 billion in OpenAI's Series C in the first half of 2026, of which $13.7 billion in the June quarter. NVIDIA has a letter of intent to invest up to $100 billion in OpenAI as 10 gigawatts deploy. AMD issued OpenAI a warrant for up to 160 million shares against a 6-gigawatt commitment. Alphabet has agreed to invest up to $40 billion in Anthropic alongside a TPU capacity deal. And NVIDIA's own 10-K notes that "one AI research and deployment company contributed to a meaningful amount of our revenue purchasing cloud services from our customers."

Two readings are available, and both are partly right.

The benign reading: vendor financing is what capital-intensive industries have always done when the customer's asset life is long and the supplier's information advantage is large. Aircraft, telecom equipment, rail. It is efficient pre-funding, and the relevant test is simply whether revenue eventually arrives from outside the circle. On that test, Microsoft's $678 billion of commercial RPO and Alphabet's $513.9 billion of cloud backlog are the strongest available evidence that it does.

The uncomfortable reading: the same structure inflates every participant's reported results simultaneously, and it does so through accounting channels that are individually defensible. NVIDIA books a $15.9 billion gain on equity stakes whose value depends on the AI capex cycle its own products drive. If the cycle turns, the revenue falls and the investment portfolio falls together, and the correlation is not incidental — it is causal in both directions. That is a genuine amplifier that a diversified industrial supplier would not have.

Circularity is a volatility amplifier, not a solvency question, for NVIDIA specifically. NVIDIA has $50.3 billion of cash and marketable securities, $7.5 billion of long-term debt, and generated $50.3 billion of operating cash flow in one quarter. It is the counterparties further down — the debt-financed neoclouds, with GPU-collateralisedBorrowing secured against the chips themselves, so the lender's protection is the resale value of used GPUs. It works while a second-hand Blackwell rack is worth something; if that price falls, the collateral and the borrower's business model weaken at the same moment and for the same reason. borrowings and residual-value assumptions — where circularity could become a credit event. CoreWeave's Form 10-Q shows total debt, net of discount and issuance costs, of $24.86 billion at 31 March 2026 — $7.55 billion of it current — against quarterly net interest expense of $536 million and an operating loss of $144 million (CoreWeave Form 10-Q, quarter ended 31 March 2026). Roughly $7.5 billion falls due inside twelve months against a company that has not yet earned an operating profit. Observed fact — issuer filing A neocloud credit accident would not impair NVIDIA's balance sheet. It would impair the second-hand price of a Blackwell rack, and that is the number that sets everyone's depreciation schedule.

22
The threats, name by name

Figure 19 · Evidence: as cited in each card, all from the named company's own most recent quarterly release or SEC filing. Method: Verdict pills are report-authored classifications of the threat each name poses to NVIDIA's rent, not investment recommendations on those names. Metrics are as-reported for each company's most recent quarter, which end on different dates. Synthesis: The threat set divides cleanly into merchant competitors (Google, Broadcom, AMD) that can compress NVIDIA's price, and captive programmes (Microsoft, Meta, and to a degree Amazon) that only remove volume.

23
Who takes the next dollar — the margin question

Ask not who has the best chip. Ask who, when the end customer pays $1 for an AI system, has the contractual right to take their cut first.

The answer has changed. Two years ago the sequence was: TSMC takes a wafer price set by a foundry duopoly, memory takes a commodity price set by a glut, and NVIDIA takes everything else. Today TSMC still takes a wafer price at a 67.7% gross margin, and memory takes a price set by take-or-pay contracts with floors at an 84.6% gross margin, and NVIDIA takes what is left — which, so far, has been enough to expand its own margin to 74.9%, because the end customer has been willing to pay whatever was asked.

The bottleneck test, applied to the memory node: who controls it — three firms, of which two are Korean. How durable — HBM4 requires bonding precision at close to atomic scale and a co-developed logic base dieThe controller chip sitting underneath a stack of memory, which manages how data moves in and out of it. In HBM4 it has to be designed jointly by the memory maker and the accelerator designer, so the two firms are locked into each other's roadmaps years ahead — one reason the list of qualified suppliers stays short., which is why the qualification list is short. Can it be replicated — not inside the horizon. And what happens to NVIDIA's rent if this node doubles? If HBM supply doubles, memory prices fall toward the floors NVIDIA has already contracted, not below them. NVIDIA captures less of the relief than a spot buyer would.

Now the reverse scenario, which is the one that matters. Suppose end demand cools by 20%. Memory prices are floored by contract; NVIDIA's input cost per system barely moves. NVIDIA's customers, holding cancellable purchase orders and facing their own depreciation questions, push price. NVIDIA's own $119 billion of supply commitments — $95 billion of it payable within fiscal 2027 — cannot be unwound quickly; the FY2026 experience gives the template, where a demand shock produced a $4.5 billion inventory and purchase-obligation charge that cost 11 percentage points of quarterly gross margin.

Evidence: Micron Form 10-Q quarter ended 28 May 2026 (take-or-pay structure, floor and ceiling bands, floor-price margin statement); NVIDIA FY2026 10-K Item 1A (cancellable purchase orders) and Q1 FY2027 10-Q Note 10 ($119bn commitments); Microsoft FY2026 10-K ($678bn commercial RPO); Alphabet Q2 2026 10-Q ($513.9bn Google Cloud backlog); TSMC 2Q26 6-K. Method: The "demand cools 20%" column is a report-authored scenario applying the disclosed contractual mechanics; no probability is assigned and no revenue figure is forecast. Synthesis: NVIDIA sits at the one point in the chain where costs are contracted and revenues are not. That is the structural weakness the current margin conceals.

Dell is the fourth party in this chain, and it is the one nobody looks at. It shipped $16.13 billion of AI-optimised servers in the quarter ended 1 May 2026, up from $1.88 billion a year earlier. Its company-wide operating margin on that was 8.3%, and it told shareholders that gross margin rate declined "due to a shift in mix towards our AI-optimized servers offerings" while "the notable inflationary environment for component costs will persist throughout the remainder of Fiscal 2027" (Dell Form 10-Q, quarter ended 1 May 2026). Read the two disclosures together: the integrator moves the same racks NVIDIA designs, absorbs the same memory inflation, and earns an operating margin roughly one-eighth of NVIDIA's. Observed fact — scope note: Dell's 8.3% is a company-wide operating margin across ISG and CSG, not an AI-server margin, which Dell does not disclose

Arista, one layer sideways, says the same thing in its own words: "supply chain inflation and material scarcity, such as the tightening of supply conditions in the memory and silicon markets, have continued to put pressure on our gross margin." Two independent public companies that buy the same components as NVIDIA report that memory inflation is compressing them. NVIDIA reports margin expansion over the identical period. That divergence is the pricing-power test, and NVIDIA passes it — today.

That is the cleanest available demonstration of where value is captured versus where it is merely handled. Assembly, logistics, service and financing of an AI rack are worth single-digit margins. Design of the fabric, the switch silicon and the software that schedules it is worth sixty-five. The memory inside is worth eighty-five. Value creation is spread across all three; value capture is not, and the ordering is set by which layer has an alternative and which does not.

The consequence chain, two steps out. If this is right, the memory suppliers have done something more consequential than earn a good quarter: they have permanently changed where cyclicality lands. In every prior semiconductor cycle, DRAM absorbed the shock and the fabless designers were relatively protected. The contracts written in 2026 invert that. The next downturn should be gentler for Micron and SK hynix and sharper for whoever buys from them at volume. It rests on disclosed contract terms, and it is falsifiable: if memory gross margins fall below 55% in a quarter in which NVIDIA's stay above 70%, it is wrong. Inference from disclosed contract structure — Moderate confidence

24
Exogenous risk — export controls, supply, power, antitrust

Export controls: a written-off asset with option value. Already covered in section 13; the investment translation is short. China is 5.6% of revenue, guidance assumes zero China data-centre compute, and the January 2026 BIS rule grants case-by-case review conditional on certifications that bind precisely while capacity is tight. Downside is close to zero because it is already excluded. Upside is real but small and slow. The genuine tail risk runs the other way — the FY2026 10-K's warning that controls "may increase investment in foreign competitors, which would be less likely to be restricted by U.S. controls" is the company telling shareholders that policy is subsidising Huawei and its peers.

Supply: the constraint is loosening, and that is not unambiguously good. Everything already argued in section 9 applies. One dated marker: SK hynix has finalised long-term agreements with around ten customers and Samsung has begun HBM4 mass sales for Vera Rubin, which means the HBM supplier base for NVIDIA's next platform is three-wide rather than one-wide. Better for NVIDIA's supply security, worse for its exclusivity — a three-supplier HBM market is also a three-supplier market for Google's, Amazon's and AMD's accelerators.

Power: the real 2027–2028 gate. NVIDIA's own 10-Q names data centres, energy and capital as constraints on its revenue, and singles out "less-capitalized companies" as those most likely to fail to finance. Grid interconnection timelines of 24–36 months in major markets mean that the capacity being ordered in 2026 is being sited against energisationThe moment a completed data centre is actually connected to the grid and can draw power. Until then the building, the racks and the chips inside it earn nothing — which is why the queue for a grid connection, not the queue for silicon, is where the constraint moves next. dates in 2028. Estimated — industry reporting The practical implication for the equity: a power-constrained slowdown looks exactly like a demand slowdown in NVIDIA's reported numbers, but has completely different duration. Distinguishing them in real time will be the hardest analytical task of the next two years.

One measurable read-through on that constraint: Vertiv, which supplies the power and thermal-management equipment a data hall needs before a rack can be energised, grew net sales 24.1% to $3,274.3 million in the quarter ended 30 June 2026, and attributed part of the shortfall against volume to "temporary supply chain congestion and multi-phased project execution" (Vertiv Form 10-Q, quarter ended 30 June 2026). Compare that with hyperscaler capex growth of roughly 55% over the same half. The gap between money committed and megawatts delivered is visible in the equipment layer, and it is widening. Inference — Vertiv serves the whole data-centre market, not AI alone, so the comparison is directional

Antitrust: not a numbers risk yet, but a structure risk. On 23 March 2026 Senators Warren and Blumenthal wrote to Jensen Huang arguing that NVIDIA, which they say "controlled about 90% of the market for graphic processing units," had "effectively acquired Groq in all but name" through a structure designed to "skirt the typical antitrust premerger notification and review process," with a response deadline of 3 April 2026 (Senate press release, 23 Mar 2026). No enforcement action has been publicly announced as of this report's cutoff. Known unknown

The material point is not the letter. It is what the transaction says about NVIDIA's own assessment of the threat. A company that believed inference ASICs were harmless would not pay $17.0 billion of disclosed consideration — $14.4 billion of it goodwill attributed to "the workforce and future development of the licensed technology" — for a licence and a team, and then ship the result as a named rack element within six months. The Groq deal is the clearest available evidence of where NVIDIA thinks its own moat is thinnest, and it points at inference silicon, not at training GPUs. Whether the structure survives regulatory scrutiny is a second-order question; the revealed preference is the finding.

25
Financials and capital allocation — what changed this year

Fiscal 2026 revenue was $215.9 billion, up 65% from $130.5 billion, with Data Center at $193.7 billion — 89.7% of the company; the fourth quarter alone delivered $68.1 billion of revenue and $62.3 billion of Data Center revenue, up 75% year on year, at a 75.0% GAAP gross margin (NVIDIA Q4 FY2026 results release). Full-year gross margin fell to 71.1% from 75.0% as the model shifted "from offering Hopper HGX systems to Blackwell full-scale datacenter solutions" and absorbed the $4.5 billion H20 charge. In the April 2026 quarter, revenue of $81.6 billion produced a 65.6% operating margin and $50.3 billion of operating cash flow.

Three capital-allocation facts changed the character of the company in a single quarter. None has been widely absorbed.

The dividend went up twenty-five fold. On 18 May 2026 the board raised the quarterly dividend from $0.01 to $0.25 per share and added $80 billion to the buyback authorisation. NVIDIA returned approximately $20 billion in the quarter. On roughly 24.2 billion shares, the new dividend is about $6.1 billion a year — trivial against cash flow, but the signal is not trivial. A company that believed it could deploy every marginal dollar into capacity at 75% margins would not be establishing a dividend. This is a maturity signal, dressed as a shareholder-friendly gesture.

The obligations became large and dated. $119 billion of manufacturing, supply and capacity commitments, $95 billion of it payable in the remainder of fiscal 2027; $30 billion of multi-year cloud-service commitments; $32.4 billion of data-centre leases expected to commence between Q2 FY2027 and FY2033, "primarily for data center leases to support our research and development efforts." Committed supply is roughly 47% of trailing-twelve-month revenue. Derived: 119,000 ÷ 253,491 NVIDIA is renting its own compute at scale — a fabless designer that now has an infrastructure liability.

Earnings quality diverged from operating quality. $15.9 billion of the quarter's pre-tax income was investment gains. This is disclosed, excluded from non-GAAP, and entirely legitimate. It is also pro-cyclical with the business, and it means the headline 71.5% net margin should not be compared with any historical figure without adjustment. On an operating basis, 65.6%, the business is more profitable than almost anything of its size in history, and that is the number to underwrite.

26
What ~$5.25 trillion actually prices in

At $216.75 on 11 August 2026 the market pays about 33x trailing earnings and roughly 22x forward, on a company whose most recent quarter grew 85% (stockanalysis.com, 11 Aug 2026). Trailing twelve-month revenue is $253.5 billion and trailing net income $159.6 billion, so the shares trade at about 20.7x sales. Derived from the four most recent quarterly filings

The multiple is not, on its face, demanding. That is what makes the analysis interesting. Nobody has to believe in miracles to own this at 22x forward earnings. What they must believe is something more specific and much harder: that the 75% gross margin is still there in 2029.

Run the arithmetic explicitly. Annualising the guided July quarter gives a $364 billion revenue run-rate. Hold net margin at 50% — below the current 55% ex-investment-gains level, allowing for some mix and tax drift — and a $364 billion revenue base earns about $182 billion, or roughly $7.52 a share on 24.2 billion shares. At today's price that is 28.8x an annualised current run-rate. The market is therefore paying a modest premium to the run-rate and asking for growth to justify the rest.

This is not an expensive stock on any conventional measure, and the frequent claim that "$5 trillion prices in perfection" does not survive the arithmetic. What the price does embed is an assumption that a 75% gross margin, in a business whose inputs are contractually floored and whose three largest customers are 54% of revenue and are all building substitutes, persists for another four years. That assumption is neither obviously right nor obviously wrong. It is simply the whole investment.

27
The bear case, steelmanned — then dismantled

Here is the strongest version of the opposing worldview, argued to persuade rather than to be knocked down.

Figure 23 · Evidence: NVIDIA Q1 FY2027 10-Q (concentration, commitments, inventory, investment gains) and FY2026 10-K Item 1A (cancellable orders, H20 charge); Alphabet and Meta Q2 2026 10-Qs (debt issuance); Meta newsroom 11 Mar 2026; AWS Trainium disclosures; UALink Consortium 2.0. Method: The bear case is stated as its strongest advocate would state it, using only sourced facts. Synthesis: Every load-bearing element of the bear case is disclosed and true; the question is what it implies, not whether it is accurate.

Now the dismantling. It does not deny a single fact above.

The bear case's central error is a category error about what the hyperscalers are substituting. Read the disclosures on their own terms. Meta describes "a portfolio approach… while keeping our own MTIA custom silicon at the center," with MTIA 400/450/500 aimed "primarily… to support GenAI inference production." Microsoft's programme is first-party only, with no external availability disclosed. Amazon's Trainium anchors one customer at enormous scale — and its next generation is designed to plug into NVIDIA's fabric. In every case the substitution target is steady-state inference on a known model, which is precisely the workload where a fixed-function ASIC wins and precisely the workload NVIDIA has the weakest structural claim to. None of these programmes is substituting for frontier training, for multi-tenant clouds serving heterogeneous customer models, or for the sovereign and enterprise buildouts that are now half of NVIDIA's Data Center revenue and growing 74%.

Second, the bear case treats capacity substitution as if it were margin substitution. It is not, while supply is short. A hyperscaler that moves 30% of its inference to MTIA does not force NVIDIA to cut price; it frees NVIDIA's constrained supply for the ACIE buyers queuing behind it. That is why NVIDIA's gross margin expanded rather than contracted through the exact period in which every custom-silicon programme reached production. The bear thesis has already had its test window, and the margin went the other way. Observed fact — gross margin 71.5% underlying in Q1 FY26 to 74.9% in Q1 FY27

Third, on cancellable orders and the H20 precedent: the analogy is weaker than it looks. The H20 write-off was caused by a regulatory shock that instantaneously voided a specific SKUStock-keeping unit — one specific product variant, as distinct from the product line. The H20 was a single China-only version of a chip; a rule that killed it did not touch anything else NVIDIA sold., not by demand evaporating. It is evidence of policy risk, which this report treats as real, rather than evidence of demand fragility.

Where the bear case genuinely lands, and where this report concedes it: the margin asymmetry in section 23, the concentration trajectory in section 21, and Google's reclassification from captive to merchant. Those are not answered by any of the above. They are why the verdict is a hold rather than a buy.

28
Alternatives considered and rejected

Evidence: as cited throughout Parts I and II. Method: Each alternative is stated as its strongest advocate would, then tested against a specific disclosed fact; the reopening condition is written to be observable and dated. Synthesis: The rejected readings cluster at the two extremes, which is usually a sign that the evidence supports a conditional rather than a directional view.

29
Second- and third-order effects

The cheaper inference gets, the more the fabric matters. Already argued in section 18, and it is the most important "so what" in the report. Falling cost per token expands token volume and pushes models toward disaggregated serving across many nodes, which converts a compute problem into a networking problem. NVIDIA's least-copied asset therefore appreciates as its most-copied asset commoditises.

The annual cadence is quietly hostile to NVIDIA's own customers. A twelve-month architecture cycle obsoletes rivals — and also obsoletes the Blackwell rack a neocloud financed over six years. NVIDIA is simultaneously the cause of, and the beneficiary of, the depreciation debate. Third-order: if hyperscalers respond by shortening useful lives, their reported cloud operating income falls, which tightens the capex approval that funds NVIDIA. The cadence has a self-limiting property nobody prices.

Merchant TPUs change Alphabet's incentive on price, not just on volume. As long as TPUs were captive, Google's optimal behaviour was to build enough for itself and buy NVIDIA for Google Cloud customers who asked. Once TPU systems are a revenue line with external on-premises customers, Google's optimal behaviour is to win share — and it can price at any level above marginal cost because the R&D is already sunk against internal use. That is the classic dynamic that destroys a merchant supplier's pricing power, and it is now visible in a 10-Q rather than in speculation.

Vendor financing transfers cycle risk from the buyer's balance sheet to the supplier's income statement. NVIDIA's $15.9 billion of quarterly investment gains are the upswing of this. The downswing runs the same way, and it arrives in the same quarter that revenue disappoints. Diversified industrials do not have this correlation; NVIDIA has chosen it.

Memory's new contract structure will outlast this cycle and reshape the next one. If take-or-pay with floors becomes the industry norm, every fabless designer's cost base becomes less cyclical and less controllable at once. The long-run winner of that change is the firm with the most pricing power downstream — which, on today's evidence, is still NVIDIA, but by a narrower margin than in 2024.

30
Falsifiers and dated predictions

Evidence: Each prediction extends a disclosed trend cited earlier: networking growth of 199% y/y; gross-margin range 71.1%–75.0% across FY2025–Q1 FY2027; Alphabet's Q2 2026 TPU-system disclosure; AWS's Trainium4 NVLink Fusion statement; concentration of 54% in Q1 FY2027; Micron's floor-price commentary; NVIDIA's zero-China guidance assumption; the Warren/Blumenthal letter of 23 Mar 2026. Method: Each is written so a single future filing or public statement settles it. Confidence tags follow the six-level scale used throughout. Synthesis: Predictions 1, 4 and 6 are the ones that most directly test this report's central claim that rent is concentrating in fabric and migrating upstream to memory.

Figure 26 · Evidence: NVIDIA CFO Commentary Q1 FY2027 and press release 31 May 2026; AMD Q2 2026 press release and OpenAI/Anthropic announcements; Alphabet Q2 2026 10-Q; UALink specification page; AWS Trainium4 disclosure. Method: Only dated, publicly scheduled or issuer-stated events are listed. Synthesis: The 2027 cluster is where the competitive picture resolves — three of the five falsifiers become observable within eighteen months.

31
The verdict, and the kill criteria

Figure 27 · Evidence: price and multiples from stockanalysis.com, 11 Aug 2026; gross margin and concentration from NVIDIA's Q1 FY2027 10-Q and CFO Commentary. Method: A structural verdict on the business and its economics, not a price target and not a trade recommendation. Synthesis: Hold rather than buy because the two heaviest debates resolve in opposite directions — moat durability supports the position, demand-and-margin duration does not yet justify paying up.

Figure 28 · Evidence: NVIDIA Q1 FY2027 10-Q Notes 10 and 13; FY2026 10-K Item 1A and Item 7; hyperscaler Q2 2026 filings. Method: Each criterion is written to be settled by a single future disclosure. Synthesis: The buy conditions and kill criteria are deliberately asymmetric in kind — the upgrades require evidence of pricing power independent of scarcity, the exits require evidence that the fabric or the margin has broken.

Scarcity flatters everyone. The test of a moat is what the margin does the first time the queue disappears.

On distinguishing a lead from an annuity

Evidence register

Every source below was opened and read in preparing this brief. Tier 1 = issuer filings, issuer releases and regulator publications. Tier 2 = reputable trade, wire or named-analyst work. Tier 3 = aggregated or single-source data used only where flagged. Event dates and publication dates are distinguished in the description. Where a single filing carried several distinct disclosures, the sections actually read are itemised in the description rather than listed as separate rows — the NVIDIA 10-Q alone supplied six (MD&A, Notes 6, 10, 13 and 14, and Item 1A) and the FY2026 10-K seven. Evidence cutoff: 11 August 2026.

Method note on derived figures. Every calculation in this brief is shown where it is used. The recurring ones: Micron gross margin 35,056 ÷ 41,456 = 84.6%; Broadcom gross margin 15,415 ÷ 22,187 = 69.5%; SK hynix operating margin 60,542.6 ÷ 79,318.7 = 76.3%; NVIDIA Q1 FY2027 operating margin 53,536 ÷ 81,615 = 65.6%; NVIDIA net margin excluding equity gains (58,321 − 15,936 × (1 − 0.166)) ÷ 81,615 = 55.2%; China share 4,550 ÷ 81,615 = 5.6%; trailing-twelve-month revenue 81,615 + 68,127 + 57,006 + 46,743 = $253,491m and net income $159,613m; supply commitments as a share of TTM revenue 119,000 ÷ 253,491 = 47%; Microsoft calendar H1 2026 capex 115.95 − 80.15 + 30.88 = $66.68bn; Figure 21 cells = revenue × 0.50 ÷ 24.2bn shares × multiple. All computed with a calculator, not estimated.

Not verified / not load-bearing

The following were encountered in research but could not be confirmed against a primary source opened in preparing this brief. None of them carries a conclusion, a verdict, a figure value or a prediction anywhere in this document. They are listed so a reader can see exactly what was excluded and why.

This document is an internal structural assessment of NVIDIA's technology position and equity economics. It is not investment advice, not a recommendation, and not a solicitation. Verdicts are structural classifications, not trade calls, and no price target is expressed or implied. Evidence cutoff: 11 August 2026; developments after that date are not reflected.